ECC Techniques for Enabling DRAM Caches with Off-Chip Tag Arrays
Error correcting codes (ECCs) are widely used to provide protection against data integrity problems in memory. With continue scaling of technology and lowering of supply voltage, failures in memory are becoming more prevalent. Integrating a large-scale DRAM cache is a promising solution to address the memory bandwidth challenge, and this is becoming more compelling with 3D-stacking technology. How to design efficient ECC for new memory usage within the restrictions of commercial DIMMs has emerged as a new challenge. This paper proposes two new ECC techniques; Hybrid ECC and Direct ECC Compare.