Memory Controller–Level Extensions for GDDR5 Single Device Data Correct Support
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Support for Reliability, Availability, and Serviceability (RAS) is one of the quintessential features of computing systems targeting the server and missioncritical markets. This paper proposes a method to provide SDDC (single device data correct) support at the memory controller level for memory technologies that inherently have no RAS support for memory contents protection. Specifically, it focuses on how to provide single-device SDDC support for GDDR5 memory.