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STTRAM Scaling and Retention Failure

Authored on: May 24, 2013 by Helia Naeimi et al

Technical Paper

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Ever larger on-die memory arrays for future processors in CMOS logic technology drive the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. The STTRAM scaling roadmap for last level cache (LLC) and how much dimensional scaling is feasible with this technology is studied. This paper will show that the main limitation on STTRAM dimensional scaling will be posed by retention time failure.
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