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An Independent Evaluation of Floating-Point DSP Energy Efficiency on Altera 28 nm FPGAs

Authored on: Feb 1, 2013

Technical Paper / Case Study

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Altera recently introduced a floating-point design flow intended to streamline the process of implementing floating-point DSP algorithms on Altera FPGAs, and to enable those designs to achieve higher performance and resource usage efficiency than previously possible. In a previous white paper, BDTI performed an independent analysis to assess the performance of Altera FPGAs in demanding floating-point DSP applications and evaluated the effectiveness of Altera's floating-point DSP design flow. Subsequently, BDTI performed an independent evaluation of the power consumption and energy efficiency of Altera FPGAs for demanding floating-point DSP applications. This white paper presents BDTI's findings from this follow-up evaluation.

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