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Low-Cost Implementation of High-Performance PCIe Gen2 Hard IP

Authored on: Mar 7, 2013 by Graham Baker et al

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Once the domain of high-end processors and soft intellectual property (IP) cores in FPGAs, the PCI Express (PCIe) specification has evolved to the inclusion of hard IP cores within the FPGAs. Historically, support for these advanced speeds and throughput has been the domain of the high-performance and midrange FPGAs. Altera first offered a hard PCIe IP block in Stratix IV FPGAs (2008), but now supports PCIe Gen2x4 IP in even the low-cost Cyclone V FPGAs, enabling smaller package implementations and fewer power rails, and lowering total power consumption while taking advantage of the performance gain.
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