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Analyzing and Debugging Performance Issues with complex ARM CoreLink System IP Components

Authored on: Mar 12, 2013 by William Orme, Nick Heaton

Technical Paper

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The complexity of today's SoC, with many heterogeneous processors, requires innovative on-chip interconnect fabrics to meet performance, power, and area targets. ARM's AMBA 4 brings AXI4, ACE and ACE-Lite, in addition to legacy AMBA 3 interfaces. New features such as hardware coherency and Quality of Service (QoS) in the ARM CoreLink system IP deliver software simplicity and increased system performance. However, the increase in the capabilities and services provided by the interconnects require careful configuration, programming and functional and performance verification. This paper describes technology and solutions that can accelerate this process to reduce time to market.
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