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Clock and Reset Ubiquity: A CDC Verification Perspective

Authored on: Jan 18, 2013 by Vaishnav Gorur

Technical Paper

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Today's SoC integrates a collection of peripherals, memory, graphics, networking and I/O components from a multitude of sources. These independently developed components come together to enable a rich feature set for the SoC. However, this introduces a new complexity. Components operate at clock frequency ranges that may be very different from each other. These multiple clock domains and the need for them to exchange information creates a hotbed for clock domain crossing (CDC) bugs to thrive. CDC verification is now critical to ensure that metastability is not introduced in the design. This paper offers examples that showcase the challenges in CDC verification.
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