Smart Power Hook-up Methodology for Memories on SoC
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Meeting IR drop requirements on a SoC can often be a challenging task. The worst IR drop the designer finally meets depends to a large extent on the design of the hard IPs and memories and also on how the hard blocks have been hooked up on SoC. This paper discusses a new hook up methodology for memories on SoC that helps in significantly reducing the worst IR drop on SoC and also leads to improved performance.
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