The on-chip decap required by a chip can be calculated at two stages of design:
Early Stage: Early in the design cycle based on initial power estimation
Advance Stage: At the post route stage using real design data like VCD, SPEF. Early stage analysis shows an empirical estimate of decap requirement which helps us to ensure sufficient amount of on-chip decap and impact on die area.
This paper proposes the methodology to calculate the required on-chip decap value at early stage of the design.
Freescale Semiconductor is a global leader in the design and manufacture of embedded semiconductors for the automotive, consumer, industrial, networking and wireless markets. Freescale became a... Read More
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