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Verifying Cache Coherency Protocols with Verification IP

Authored on: Oct 1, 2012 by Chris Thompson

Technical Paper

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The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced features and the extent of its support for the AMBA ACE protocol. Learn how a Reference Verification Platform (RVP) built with Synopsys' next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 ACE protocol can be used to accelerate the verification of multicore SoCs.

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