datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech

A Systematic Approach to Tester Pattern Generation and Stabilization for SoC

Authored on: Jun 29, 2012 by Prokash Ghosh, Sandip Ghosh

Technical Paper

0 0
More InfoLess Info
In a typical SoC, there are many IPs and each has its own AC characterization requirements to validate the Hardware Specification. There are many issues faced when bringing up the AC-CZ pattern on an ATE. Also, stabilizing the patterns on the ATE across PVT is a very challenging task faced by the design and test community. This paper introduces guidelines for the development of AC characterization patterns and running them on a virtual tester and an ATE.
0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page