A Systematic Approach to Tester Pattern Generation and Stabilization for SoC
In a typical SoC, there are many IPs and each has its own AC characterization requirements to validate the Hardware Specification. There are many issues faced when bringing up the AC-CZ pattern on an ATE. Also, stabilizing the patterns on the ATE across PVT is a very challenging task faced by the design and test community. This paper introduces guidelines for the development of AC characterization patterns and running them on a virtual tester and an ATE.