Improving IC Silicon Yields by Voltage Drop Based Timing Closure
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One of the primary steps in a semiconductor IC design flow is to ensure the IC meets the frequency performance goals that it has been designed for. Any wrong assumption made in closing the design timing at pre-silicon level can cause the design to completely fail at silicon or result in poor yield. This paper describes modeling the operating voltage of the cells in such a way that each of the portions of the design is timing closed at different operating voltages these portions are actually working at, by factoring in the voltage drop along the power nets in the design.