Self-timed Circuit Device Size Optimization for an Input Data Distribution
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New design techniques with energy-delay characteristics that are superior to that of the synchronous timing and control approach are needed today because the throughput of systems realized with this method is limited by the power dissipation of nanometer scale devices and the power management strategies developed to insure that they do not exceed device thermal constraints. A novel self-timed circuit device sizing approach that is based on the circuit input data distribution is proposed in this paper.
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