datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Efficient Migration of Verilog Testbenches to UVM

Authored on: Dec 1, 2011 by Mehul Kumar, Nitin Goel

Technical Paper

0 0
More InfoLess Info
This paper addresses challenges faced during the conversion of a typical IP level Verilog verification environment to a UVM-based flow with minimal efforts. This paper also offers a comparative study of Verilog code and its corresponding code in UVM environment, covering the components that are present in the Verilog environment (e.g. Driver, Monitor, Testcase). It aims to establish the proof that the two counter-parts following the methodology flow described would be functionally identical.

Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page