Efficient Migration of Verilog Testbenches to UVM
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This paper addresses challenges faced during the conversion of a typical IP level Verilog verification environment to a UVM-based flow with minimal efforts. This paper also offers a comparative study of Verilog code and its corresponding code in UVM environment, covering the components that are present in the Verilog environment (e.g. Driver, Monitor, Testcase). It aims to establish the proof that the two counter-parts following the methodology flow described would be functionally identical.
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