Design Con 2015
Welcome Guest Log In | Register

How to use C++ Model effectively in SystemVerilog Test Bench

Authored on: Oct 12, 2011 by Krunal Patil

Technical Paper

0 0
More InfoLess Info
This paper describes the methodology of effectively using C++ Models in the SystemVerilog test bench to get the higher verification coverage. This also gives a solution of overcoming the existing limitations arises because of using C++ test cases for RTL design verification.
View
 
0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page