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Shrinking SoC Design Cycles Using DesignWare Intellectual Property

Authored on: Jun 3, 2011 by Vijay Kumar Mathur et al

Technical Paper / Case Study

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The amount of IP integrated into SoCs is rapidly growing, especially when compared to the ever-shrinking time for SoC designs. IP is mostly reused from an existing IP repository or procured from third-party vendors; very rarely is it designed for a specific SoC. This makes it imperative that SoC designers choose high-quality, easily customizable IP to meet their overall system interface and power requirements.  This paper discusses how projects at STMicroelectronics successfully use a variety of DesignWare IP in a complex SoC design, and how the flexibility and features offered by these solutions helped them meet their system design goals.
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jj31750 Posted Nov 9, 2011

It's strange that having 140 KGates from coreConsultant (5148 KGates in final implementation) could be used to decide the die-size. I suspect an extra "5". Please re-read article.

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johns61 Posted Nov 15, 2011

Clearly a typo... A big one but as you pointed out, an extra "5".

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Emily.Soucy Posted Nov 17, 2011

The typo has been fixed. Thanks!

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Gaurav.Bhatnagar Posted Dec 2, 2011

Thanks for the comments and correcting the typo. Did you guys like the article? - Author (Gaurav)

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