Verification of Data Eye Width Variation in Differential Serial Protocols
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Today there are limited ways of verifying the Data Eye Width Variation in Differential Serial protocols through dynamic simulations (both RTL and GLS), leading to postponement of the same to test vehicle or post silicon. As a result, any bug creeping in at that stage leads to costly re-spins. Limited Verification is done around this area—in fact if at any verification is done, it involves: limited clock frequency ranges, limited phase variations over the eye and no eye width variation at all. This paper proposes a scheme to address some of these issues. The proposed verification scheme emulates real-time scenarios at the RTL simulation stage.
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