datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Unified Test Plan: Efficient Solution for Faster and Enhanced IP Maturity

Authored on: Aug 11, 2011 by Sachin Jain, Yogesh Mittal

Technical Paper

0 0
More InfoLess Info
With ever shrinking project timelines, it has become absolutely essential for IPs to be delivered with zero defects to SoC integrators. IP availability has always been the critical part of SoC timelines. The more mature the IP, the better it is for the SoC timelines. This paper dicusses the challenges involved to deliver a fully validated 'zero defect' IP with more emphasis on the effort to reduce the verification gap, defined as the difference between the ability to fabricate and the ability to verify. This paper addresses the planning part only and introduces the concept of a Unified Test Plan (UTP) and discusses in detail the use of the UTP to resolve the above-mentioned issues.

Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page