datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Optimizing Performance, Power and Area in SoC Designs Using MIPS Multi-threaded Processors

Authored on: Mar 28, 2011

Technical Paper

0 0
More InfoLess Info
This paper provides a brief history of hardware-based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies' multi-threading architecture and product offerings, including the latest interAptiv family of 32-bit, multi-core CPUs. The paper also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the value of multi-threading across a broad range of real-world applications.

Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page