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Modeling System Signal Integrity Uncertainty Considerations

Authored on: Jan 27, 2011 by Zhi Wong

Technical Paper

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This white paper describes signal integrity mechanisms that cause system-level timing uncertainty and how these mechanisms are modeled in the Quartus II TimeQuest Timing Analyzer for timing closure for external memory interface designs. By using the Quartus II development software v.9.1 and later to achieve timing closure for external memory interfaces, a designer does not need to allocate a separate SI timing budget to account for simultaneous switching output, simultaneous switching input, intersymbol interference, and board-level crosstalk for Altera flip-chip device families such as Stratix IV and Arria II FPGAs for typical user implementation of external memory interfaces following good board design practices.
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