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Guidelines for Constraint Random Verification

Authored on: Dec 20, 2010 by Sidhesh Patel

Technical Paper

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System on Chip (SoC) is getting more and more complex as demand is to put more functionality in single chip. Likewise, SoC verification is also getting complex, as the number of scenarios to verify grows equally or sometimes multiplicatively. Writing directed test for each scenario to cover all possible combination and cross combinations is very difficult or rather impractical as per today's time to market requirement. This article lists some guidelines to make constraint random verification strategy more successful.
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jrogers_mrcy Posted Dec 23, 2010

The whitepaper reads like a first draft of an outline. High-level concepts are discussed, but nowhere is there any real technical content in the paper.

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PranaySamanta Posted Sep 16, 2013

It is so basic. There is nothing in this paper to be called as a technical paper. :(

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