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Implementing Lowest Resource and Highest Throughput FPGA Data paths in Days, not Weeks

Authored on: Oct 18, 2010 by Arthur Torosyan

Technical Paper

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Designing FPGA datapath blocks such as filters, modulators, demodulators, direct digital synthesizers (numerically controlled oscillators), forward and inverse transforms, and equalizers is expensive, highly resource intensive, and time consuming.  Finding the optimal design for a given set of specifications is often infeasible given the time, resource, and IC price-performance constraints. Most importantly, achieving throughput rates above 200-400 MSPS is simply impossible, rendering high throughput signal processing applications off limits for FPGAs. Using GATeIC's digital datapath design, optimization, and implementation tools on configurable IP solves the problem of optimizing resource utilization on FPGAs, while achieving very high throughputs.
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giant007 Posted Oct 21, 2010

WOW, according to the paper, they can run FIR filters and NCOs at many times the maximum clock speed of the FPGA device. For example, one of the tables shows that they can push a FIR filter at 700MHz on a Xilinx device. As far as I know, Xilinx's own IP can be clocked at 450MHz max, on a Vertex 6 device. Will follow-up.

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