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Implementing Lowest Power Digital Datapaths in Days, not Weeks

Authored on: Oct 4, 2010 by Art Torosyan

Technical Paper

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Designing power and area optimal digital datapath blocks such as filters, modulators, demodulators, direct digital synthesizers (numerically controlled oscillators), forward and inverse transforms, and equalizers is expensive, highly resource intensive, and time consuming. Converging on optimal design is often infeasible.
Using GATeIC's digital datapath design, optimization, and implementation tools on configurable IP solves the problem of optimizing power and area, while reducing cost and spec-to-GDSII time for ASICs, and minimizes resources on utilization FPGAs. ASIC implementations using GATeIC's tools and IP, one in 180nm and another in 65nm, reduced power by 60% and 40%, and area by 30%.
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giant007 Posted Oct 6, 2010

wow, if they can really do what the paper says, this is a game changer. will try completing one of the filter spec sheets to see the power results.

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rafayel17 Posted Oct 7, 2010

Very well written... got me thinking...

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CKachi Posted Oct 7, 2010

really clearly written ...well explained!

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Dr DSP Posted Nov 27, 2010

The weakness of this approch seems to be the introduction of perturbations and rerunning the design thru the tool flow. If my design takes hours to run (like on a big FPGA) this could take a LONG time. Am I missing something?

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