Welcome Guest Log In | Register

Asynchronous Processor Design Evolution

Authored on: Mar 2, 2010

Technical Paper

0
More InfoLess Info
This paper discusses how clockless design methodologies can improve the power and silicon  efficiency of processors manifold. For fully programmable processors, moving to a clockless design within the same silicon technology can provide power consumption benefits similar to those accruable moving down four geometry nodes like moving from 90nm to 22nm. Additionally, a clockless implementation can also be quite efficient from a silicon perspective. The techniques described herein are technology node independent and the gains achievable are sustainable from one geometry node to another.
View
 

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page