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Asynchronous Processor Design Evolution

Authored on: Mar 2, 2010

Technical Paper

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This paper discusses how clockless design methodologies can improve the power and silicon  efficiency of processors manifold. For fully programmable processors, moving to a clockless design within the same silicon technology can provide power consumption benefits similar to those accruable moving down four geometry nodes like moving from 90nm to 22nm. Additionally, a clockless implementation can also be quite efficient from a silicon perspective. The techniques described herein are technology node independent and the gains achievable are sustainable from one geometry node to another.
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ahshabazz Posted Aug 9, 2011

2/5 stars. Clockless logic - same issues as before: Only useful in military (budget); not always cross-platform compatible (EDA); not easily implementable; lots of up potential; few signs of global adoption (weak advocacy system).

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