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Breaking the 2 Giga Access Barrier: Overcoming Limited I/O Pin Counts

Authored on: Jun 23, 2010 by Michael Miller

Technical Paper

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Projected Internet traffic will approach 1 Zettabyte (1 trillion Gigabytes) per year. To support this amazing trend, the next generations of networking equipment must offer new levels of packet forwarding rates and bandwidth density. This in turn will necessitate new generations of packet processors and the memory subsystems to support these increased demands.

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Dr DSP Posted Jul 20, 2010

Excellent analysis with real world examples from Cisco and Juniper. It looks to me like this memory architecture is also a 'shot in the arm' for DSP and High-Performance computing (FPGAs and Memories used for matrix operations in financial, molecular modeling, etc applications) systems as well. Maybe video too? Any other thoughts on these possibilities?

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