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Reducing Switching Power with Intelligent Clock Gating

Authored on: Jun 4, 2010 by Frederic Rivoallon

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Xilinx introduces the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30 percent for Virtex-6 and Spartan-6 FPGA designs. Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.

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