Developing FPGA Coprocessors for Performance-Accelerated Spacecraft Image Processing
The Jet Propulsion Laboratory (JPL), a National Aeronautics and Space Administration (NASA) laboratory, has developed support vector machine (SVM) classification algorithms used on board spacecrafts to identify high-priority image data for downlinking to Earth. These algorithms also provide onboard data analysis to enable rapid reaction to dynamic events. These onboard classifiers help reduce the amount of data downloaded to Earth, greatly increasing the science return of the instrument.
This article describes an approach to implementing the Hyperion linear SVM on the Virtex-4 FX60 field programmable gate array (FPGA), as well as additional experiments that were performed using an increased number of data bands and a more sophisticated SVM kernel. These experiments demonstrate potential for more efficient, higher performance onboard classification using FPGA-embedded algorithms.