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Programmable Clock Management Increases Source Synchronous Throughput

Authored on: May 12, 2009 by Srirama Chandra

Technical Paper

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Theoretically, there is no upper limit on source synchronous channel speed. In reality, the speed of the communication path is determined by a number of factors such as clock jitter, duty-cycle distortion, and differences in the delay between the clock and data paths within the receiver. Compensating for these factors across process, voltage and temperature complicates the receiver design.

This article examines the features of a dynamically adjustable programmable skew clock chip and proposes a scheme that compensates for various limitations and enables increasing source synchronous communication speed while maintaining reliability. It considers the factors limiting source synchronous communication speed, details a dynamically adjustable skew clock chip architecture, and proposes a source synchronous communication based on it.



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