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High-Speed SERDES Interfaces In High Value FPGAs

Authored on: May 6, 2009 by Siddhartha Mohanty

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Serial interfaces are commonly used for chip-to-chip and board-to-board data transfers. As system bandwidths continue to increase into the multi-gigabit range, parallel interfaces have been replaced by high-speed serial links, or SERDES (Serializer/ Deserializer). Initially, SERDES were available as standalone ASSPs or ASICs. The last few years have seen the introduction of FPGA families with built-in SERDES. These devices offer an attractive alternative to standalone SERDES devices. However, these SERDES-based FPGAs have often been expensive, since they were offered as part of high-end (and hence more expensive) FPGA families. Lattice Semiconductor has been a pioneer in this area, and has introduced two low cost FPGA families with SERDES, the LatticeECP2M, introduced in 2007, and the most recent family, the LatticeECP3. The ECP2M and ECP3 FPGAs provide designers with the best of both worlds: a high performance, low-cost FPGA fabric with built-in high performance SERDES. These devices offer designers a low-cost integrated platform to meet their next generation design requirements. Lattice also offers customers a high performance SERDES-based FPGA family, the LatticeSC/M, which offers additional on-chip ASIC IP integration.

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