Visualizing, Analyzing and Debugging SystemVerilog Testbench Environments
SystemVerilog, and the verification methodologies that have sprung up around it, have enabled a significant leap forward in testbench automation and allow for generation of sophisticated stimulus scenarios. This level of sophistication and automation requires a corresponding leap in debug capabilities within such environments. Advanced logging and interactive inspection provide an ideal means of recording transactions from the testbench and subsequently, allowing visualization and analysis of these transactions. Automating the recording of all transactions of interest will further simplify the process by reducing the instrumentation burden on the user. Authors look at these emerging verification techniques.
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