Using on-chip networks to Minimize Software Development Costs
Today's multi-core SoCs face rapidly escalating costs driven by the increasing number of cores on chips. It is common to see code bases for chips that exceed 5 million lines of code. The software integration task alone has become a massive compatibility and verification challenge with real-time consequences to the performance of the device. Software teams are racing to create finely tuned systems, only to have much of their work undone by last minute core or standards changes.
The ability to configure, verify, and model the interconnect and predicted data flows for the SoC early in the architecture research enables developers to understand what performance they can expect and how to manage system resources along the way. Sonics will discuss how developers can now get a reliable "preview" capability flexible enough to change during the chip development cycle, so that they can more readily plan and execute system management schemes upfront—while significantly minimizing re-engineering efforts, and ultimately costs, as the chip is developed.
Please disable any pop-up blockers for proper viewing of this paper.