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Tackling I2C Development Complexities Using Innovative Tools

Authored on: Aug 19, 2009 by Iser Flaum

Technical Paper

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Validating device compliance to the I2C protocol is a difficult task. Understanding how a device reacts under non-ideal conditions such as stress testing is even tougher. This paper describes an I2C bus analysis tool that helps ease I2C bus compliance and interoperability with unique features such as parametrics testing, glitch injection, timing skew, and master/slave emulation.

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