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Reducing Interrupt Latency Through the Use of Message Signaled Interrupts

Authored on: Jan 8, 2010 by James Coleman

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Embedded systems have traditionally been much more sensitive to both the interrupt latency and Central Processing Unit (CPU) overhead involved in servicing interrupts as compared to conventional Personal Computers (PC). Message Signaled Interrupts (MSI) represent the third generation of interrupt delivery methods for IO (Input/Output) devices, providing many benefits, including a significant reduction in interrupt latency. Intel architecture, consisting of a CPU, memory controller, and an IO controller, can provide the embedded developer with a competitive platform for embedded designs. Linux, a mature yet flexible open source operating system, has been extensively optimized for Intel architecture, providing a robust interrupt framework supporting MSI.

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