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SEmulation: Turbocharging the FPGA Development Process

Authored on: Apr 12, 2007

Technical Paper

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With the SEmulator, Gleichmann Electronics Research introduces a new method of FPGA/ASIC design, which promise shorter development times and higher design security at a lower cost. With complex processor systems, complete interface structures and design, and up to 3 million ASIC gates per chip, FPGAs dominate the semiconductor market with their flexibility and reconfigurable architecture. Time pressures on the engineer with a short design cycle do not allow for failures. Every revision costs time and money, so the functions and responsiveness of the finished semiconductors have to be right the first time after silicon synthesis.

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