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Run-Time Energy Estimation in System-on-Chip Designs

Authored on: Oct 22, 2007 by J. Haid et al.

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In this paper, a co-processor for run-time energy estimation in system-on-a-chip (SoC) designs is proposed. The estimation process is done by using power macro-models, thus making analogue measurement equipment obsolete for the software engineer once the SOC design is characterized. Compared to sampling-based profiling systems, the performance overhead of energy profiling is lower. This is because the energy estimation is done completely parallel to the functional units residing on the SOC.

The proposed methodology can be used for run-time power optimization and in-system energy profiling. The co-processor was evaluated on an SOC for MPEG layer III audio decoding and the experimental results show a maximum relative error of <5%.

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