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A Methodology for Performance Analysis of Network-on-Chip Architectures for Video SoCs

Authored on: Feb 26, 2009 by Krishnan Srinivasan

Technical Paper

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Silicon for next-generation video processing has become extremely intricate and complex. Most high-end SoC (System-on-chip) architectures now consist of tens of heterogeneous processing engines and memory units. There is increasing dependence of the SoC on the interconnection network, which is fueling the need for performance analysis of the interconnection network, requiring designers to analyze the system performance as a whole, not simply in isolation. An interconnection network provides the infrastructure for these processing engines and memory units to communicate seamlessly in parallel. With increased system complexity, the overall performance is progressively determined by the ability of the interconnection network to provide sustained data bandwidth to the engines, and at the same time, meet the real-time performance goals of latency-sensitive traffic. In this paper, Sonics presents an effective methodology for performance analysis of the interconnection network, with special emphasis on video and multimedia benchmarking.

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