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Signal Integrity and Clock System Design

Authored on: Feb 27, 2009 by Allan Liu

Technical Paper

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Signal integrity is the art of getting a signal from point A to point B with minimum distortion to that signal. The recent attention on this subject stems from the necessity to build systems with ever increasing throughput and from silicon manufacturing advances in geometry scaling that are causing system-level effects (such as crosstalk, transmission line effects and voltage drops) to manifest themselves on the chip level in a detrimental way. The vast amount of literature on this subject almost exclusively references, and correctly so, high-speed signals that operate at 1 gigabit (Gb) per second or higher. These signals are the most sensitive to these limitations and thus should receive the most attention. However, what the industry neglects is that the quality of these high-speed signals is highly dependent on the quality of the input reference clock that is used to generate these high-speed signals. The design of the clock network is equally deserving of attention on the subject of signal integrity.

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