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FPGA/PCB Pin Synchronization: How to Overcome the Increasing Management Complexity

Authored on: Nov 20, 2007 by Marty Hauff

Technical Paper

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Pin- and part-swapping has long been used by electronics designers to decrease printed circuit board (PCB) routing complexity. But the accelerated adoption of field programmable gate arrays (FPGAs) has placed new pressures on traditional PCB design flows. Yesterday's task of exchanging a few gates within an IC package or the connections to a couple of resistor arrays has been traded for today's task of managing several hundred pin swaps across one or more FPGA devices and synchronizing those changes with the FPGA design. As a design progresses through multiple iterations, the task of synchronizing the data and pins becomes increasingly time-consuming.

This paper examines traditional design processes and their efficiency in handling FPGA-based designs, exploring ways in which board-level designers can harness the benefits of FPGAs without being overwhelmed by their complexity. Of particular interest is the management of pin-swapping data across schematic, PCB and FPGA design domains.



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