datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Next-Generation Signoff Analysis Tackles Electrical, Physical, and Manufacturing Challenges

Authored on: Jan 16, 2008 by Chin-Chi Teng and Rahul Deokar

Technical Paper

0 0
More InfoLess Info

The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle. At issue are the levels of validity and confidence that can be reached with today's integrated circuit (IC) design closure and signoff methodologies.

This paper looks at some of the electrical, physical, and manufacturing challenges of current signoff analysis methods, and proposes new ways to improve productivity and performance at the 45nm process node. The paper also describes the concept of a system-on-chip (SoC) functional verification kit based on a comprehensive plan-to-closure methodology, which enables the effective adoption of advanced verification technologies and techniques.



Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page