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Off-Chip ESD Protection Anticipates IC Scaling

Authored on: Jan 22, 2008 by Bill Russell and Tim Puls

Technical Paper

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As next-generation transceivers and digital communications integrated circuits (ICs) scale to smaller geometries, the challenge for IC manufacturers to maintain reasonable levels of on-chip electrostatic discharge (ESD) protection grows. Proposed decreases in on-chip ESD protection mean that system designers must be more focused on building ESD protection into their designs.

This paper discusses the increased sensitivity of ICs that will result from the decreases and the need for system protection with more robust off-chip transient voltage suppression. Solutions are discussed, including the use of TVS diodes, board layout considerations, and device selection.



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