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Using SystemVerilog Assertions in Gate-Level Verification Environments

Authored on: Jun 23, 2008 by Mark Litterick

Technical Paper

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Real-world requirements such as multiple clock domains and low-power modes of operation, including frequency and voltage scaling, often necessitate gate-level System-on-Chip (SoC) verification environments to complement the standard RTL-based simulations. If the verification environment relies on assertion-based checkers to validate grey-box operation, then gate-level simulations will also benefit from reuse of these assertions.

This paper provides an overview of the problems related to gate-level timing and connectivity with a focus on how these affect the operation of the SVA code. A methodology is presented that enables reliable operation and reuse of the SVA in simulation environments that support RTL and gate-level implementations of the device-under-test. The paper also discusses SVA timing checks that can be added to the gate-level environment to improve checking and coverage.

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