datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register | Benefits

Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions

Authored on: Jun 10, 2008 by Mark Litterick

Technical Paper

0 0
More InfoLess Info

Recent advances in automated formal solutions for verification of clock domain crossing (CDC) signals go a long way towards reducing risk of clock-related defects in multi-clock system-on-chip (SoC) devices. However, the vast majority of multiple clock-domain devices still utilize a flow that does not involve these specialized tools or formal verification techniques.

This paper presents a pragmatic alternative methodology using SystemVerilog Assertions in a simulation-based verification flow, to validate the correct operation and use of synchronizers while emulating the effects of CDC jitter in order to stress the functional operation of the rest of the device.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page