SVA@Interface (For SATA Link, Application Layer interface)
More InfoLess Info
Assertion Based Verification (ABV) has been identified as a modern and powerful method of verification increasing productivity and providing faster time to market. The System Verilog Assertion (SVA) language actively supports the implementation of Assertion Based Verification. This paper provides inputs on how system verilog assertions need and their usefulness and a case study of using SVA in verifying the SATA Link Layer and Application layer interface.