datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Strategies for ASIC Board-Level Validation

Authored on: Apr 10, 2003 by Gus Paolone

Technical Paper

0 0
More InfoLess Info
With the advent of multi-million gate System-On-a-Chip (SOC) ASIC devices, the validation effort required has become a significant challenge, and can amount to more person-months of effort than the development of the devices themselves.

This paper describes strategies for ASIC board-level validation. It presents the advantages of undertaking an open systems approach to the development of validation strategies, and highlights the opportunities that exist to maximize circuit and embedded software reuse from the validation effort for eventual deployment in the ASIC device end-user context.

A number of validation board architectures are presented, along with a discussion of how these architectures can be extended into a validation system to facilitate chipset testing.

For more information on ASIC board-level validation, visit Calyptech's Web site.



Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page