Strategies for ASIC Board-Level Validation
This paper describes strategies for ASIC board-level validation. It presents the advantages of undertaking an open systems approach to the development of validation strategies, and highlights the opportunities that exist to maximize circuit and embedded software reuse from the validation effort for eventual deployment in the ASIC device end-user context.
A number of validation board architectures are presented, along with a discussion of how these architectures can be extended into a validation system to facilitate chipset testing.
Please disable any pop-up blockers for proper viewing of this paper.