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Progressive Refinement: A Hierarchical Design Methodology for Multi-Million Gate Integrated Circuits

Authored on: Aug 13, 2003

Technical Paper

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Most integrated circuits cost too much to produce, use more power than they need to, don't perform as well as they should, and take too much time and effort to design. These problems occur because most designers make critical design decisions without knowing what impact those decisions will have on the downstream implementation process. To resolve this issue, many companies are adopting a new approach to design. This new design methodology, called progressive refinement, is based on the use of a Silicon Virtual Prototyping (SVP) tool to bridge the gap between design and implementation.

For more information on Progressive Refinement, visit Monterey Design Systems' Web site.

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