Design Con 2015
Welcome Guest Log In | Register

Capabilities to Maximize Productivity for FPGA Debug and Verification

Authored on: Oct 1, 2009 by Davin Lim and Premduth Vidyanandan

Technical Paper

0 0
More InfoLess Info

Whether your task is to verify the functional correctness of a design, ensure adequate timing performance, or to quickly bring up a hardware platform in the lab environment, efficient verification and debug typically requires evaluating the design from multiple perspectives—ranging from high-level functional characteristics to low-level performance details—each at different phases of the design flow. To effectively complete these tasks, you need a complete and well integrated set of capabilities to help you to effectively navigate through the verification and debug process. This technical digest discusses the spectrum of verification and debug tools that the ISE Design Suite puts at your disposal.

View
 
0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page