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Minimizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis

Authored on: May 25, 2009 by Venky Ramachandran

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The combined flow of automated, sequential RTL power optimization tightly linked to low-power synthesis provides designers with a highly efficient, single-pass, low-power design flow. Together this flow enables automated RTL power optimization that produces the lowest possible power implementation while achieving the required design performance goals. An automated low-power design flow has been developed by Calypto Design Systems and Cadence Design Systems which combines the automated RTL clock gating of PowerPro CG from Calypto with the low-power synthesis of Encounter RTL Compiler from Cadence.

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