Timing Closure Exploration Tools with SmartXplorer and PlanAhead
Timing Closure! This is undoubtedly one of the most challenging aspects in modern FPGA design. It is difficult to avoid this challenge when the complexity of FPGA devices doubles every 1½ years and when designers try to pack more and more functionality into a single chip.
Xilinx invests a lot of time and effort helping designers overcome such timing challenges by improving synthesis and implementation algorithms and providing graphical analysis tools.
Although FPGA tools have become easier to use while offering more and more advanced features it is difficult to anticipate all design situations. Some of them may stay hidden until the very last stages of a design cycle, appearing just before delivering the product. Regardless of their experience level, designers usually try to explore several possibilities by changing different tool options (it is much easier) before deciding to make a change in their HDL code or trying placement constraints. How can a better set of options be identified in the first place?