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Next Generation I/O Bus PCI-Express BER Test Solution

Authored on: Dec 14, 2005

Technical Paper / Product Paper

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The focus of this document is on physical layer testing on the transmitter (TX) and receiver (RX) terminal. BER testing not only provides system or chipset function checks, when properly set up it can also provide important information on TX and RX parametric capabilities. We focus here on the chipset designer and demonstrate how to implement a total BER test solution for a PCI Express chipset. We detail how to use the Agilent 81250A ParBERT for BER measurements. We provide information on how to edit patterns on this equipment, and explain its capabilities for jitter injection and tolerance testing.

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